TLV5606IDGKR TLV5606IDR Power Path Management IC DAC 10-Bit 3 or 9 us DAC Serial Input

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need for a low source impedance drive to the terminal.

Implemented with a CMOS process, the TLV5606 is designed for single supply operation from 2.7 V to 5.5 V. The device is available in an 8-terminal SOIC package. The TLV5606C is characterized for operation from 0°C to 70°C. The TLV5606I is characterized for operation from −40°C to 85°C.